Description
Title: OPENCL PROCESSING MODELS FOR FPGA DEVICES: A STUDY
Abstract: In our study, we present the outcomes of the SHA-512 algorithm’s implementation in FPGAs. The unique aspect of our work is that we used OpenCL for FPGA, a relatively new reconfigurable logic development technique, to carry out the work. We examine loop unrolling as a technique for improving OpenCL performance and contrast the efficacy of the various SIMD, Single-Work Item, and NDRange kernel implementations. We compare the metrics of the developed FPGA accelerator to the corresponding GPGPU solutions in our conclusions. To help the reader follow and expand on our survey, our paper is also accompanied by a source code repository.
Keywords: recon gurable computing, accelerated computing, high-level hardware synthesis
Paper Quality: SCOPUS / Web of Science Level Research Paper
Paper type: Analysis Based Research Paper
Subject: Computer Science
Writer Experience: 20+ Years
Plagiarism Report: Turnitin Plagiarism Report will be less than 10%
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A turnitin plagiarism report of less than 10% in a pdf file and a full research paper in a word document.
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