Description
Title: A 3D NoC ROUTING ALGORITHM AND ROUTER ARCHITECTURE
Abstract: The development of microchip technologies in recent years has made large-scale Systems-on-Chip possible (SoC). SoC design and testing are complicated by the sharp increase in processing components. An alternative technology to address the difficulties in SoC design and testing is network on chip (NoC). The NoC architecture has become a crucial one that enables one to optimize variables like power and area. Despite its applications, NoC still encounters some real-time difficulties, such as designing the best topology, application mappings chimed. We address the raintree issues on NoC in this paper, specifically designing an ideal topology and routine galgorithmandarouterdesign for the topology. First, we suggest a topology and a routing method. We demonstrate the Hamiltonian connectivity of our recursive network topology and propose a data packet transmission algorithm that is free from cyclic deadlocks and maximizes the congestion factor. Our test results demonstrate that compared to other topologies, the proposed topology performs better in terms of average latency and power. We suggest a router architecture as a final design for our 3D-NoC. Shared buffers form the foundation of the router architecture. Additionally, according to the findings of our experiments, the proposed router architecture uses less space and power than the Virtual Channel architecture.
Keywords: network on chip, 3D topology, routing algorithm, router
Paper Quality: SCOPUS / Web of Science Level Research Paper
Paper type: Analysis Based Research Paper
Subject: Computer Science
Writer Experience: 20+ Years
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